FPG𝔸SIC @fpgasic Channel on Telegram

FPG𝔸SIC

@fpgasic

FPG/A/SIC tips and tricks

#FPGA #ASIC #VHDL #verilog #IP #Xilinx #Altera

PS: also might be intresting @ipcores

FPG𝔸SIC (English)

Are you passionate about FPGA, ASIC, VHDL, Verilog, IP, Xilinx, or Altera? If so, then you've come to the right place! Welcome to FPG𝔸SIC, a Telegram channel dedicated to providing tips and tricks for everything related to Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). Whether you're a beginner looking to learn the basics or an experienced professional seeking advanced techniques, this channel has something for everyone.

Stay updated with the latest trends in FPGA and ASIC design, explore new coding techniques in VHDL and Verilog, discover innovative IP cores, and engage with like-minded individuals who share your interests. The discussions here cover a wide range of topics, from design methodologies to optimization strategies, from troubleshooting common issues to exploring cutting-edge technologies.

Join our community of FPGA and ASIC enthusiasts, where knowledge is shared, questions are answered, and connections are made. Be part of a dynamic network of engineers, designers, students, and hobbyists who are passionate about pushing the boundaries of digital design.

Don't miss out on valuable insights and valuable resources that can enhance your skills and propel your projects to new heights. Follow FPG𝔸SIC and unlock a world of opportunities in the exciting realm of FPGA and ASIC development.

PS: For even more interesting content, be sure to check out @ipcores. Join us today and let's dive deeper into the fascinating world of FPGA and ASIC technology together!

FPG𝔸SIC

11 Sep, 08:17

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

In terms of benchmarking memory, it can be done better on FPGA, rather than on CPU/GPU. When benchmarking memory on an FPGA, the benchmarking hardware engine can directly attach to the memory such that there is no noise between the targeted memory and the benchmarking engine.

With Shuhai, before implementing the concrete application that contains a particular memory access pattern on the FPGA, we are able to benchmark the corresponding memory access pattern to make sure that the memory side will not be the bottleneck.

Links:
📄 https://ieeexplore.ieee.org/document/9114755
💾 https://github.com/RC4ML/Shuhai

#memory #ddr #hbm #benchmark
@fpgasic
1,417
FPG𝔸SIC

15 Aug, 16:09

FloorSet: The First Million-Scale Dataset for SoC Design Planning.

FloorSet is aimed at advancing machine learning for floorplanning physical layouts of systems-on-a-chip (SoCs) and its sub-systems. It features 2 million synthetic benchmark circuits that capture real design constraints and objectives, all carefully sampled from actual design distributions.

FloorSet addresses key challenges of training-data availability and reproducibility in the chip-design world, driving fundamental research in large-scale constrained optimization problems.

Links:
📄 https://arxiv.org/abs/2405.05480
💾 https://github.com/IntelLabs/FloorSet

#floorplan #SoC #MLaimed #CAE #opensource
@fpgasic
2,155
FPG𝔸SIC

07 Aug, 09:09

This element is a runtime, dynamically reconfigurable, LUT5 that enables the changing of the function of the LUT during circuit operation. Using the CDI pin, a
new INIT to change the logical function.
2,108
FPG𝔸SIC

07 Aug, 09:09

Did you know that Xilinx FPGA have Dynamically Reconfigurable Look-Up Table (LUT)?
It's called CFGLUT5

Note: This component occupies one of the eight LUT6 components within a CLBM.

#UG974 #Xilinx #recongif
1,906
FPG𝔸SIC

08 Jul, 11:58

The new taste is unlocked: BiCMOS

Now IHP providing not only 𝐨𝐩𝐞𝐧-𝐬𝐨𝐮𝐫𝐜𝐞 𝐏𝐃𝐊 but also 𝐟𝐫𝐞𝐞 𝐚𝐜𝐜𝐞𝐬𝐬 𝐭𝐨 𝐌𝐏𝐖 𝐫𝐮𝐧𝐬 to turn your designs into physical chips. This service is available exclusively for non-commercial projects.

💾 https://ihp-open-ip.readthedocs.io/en/latest/

#IHP #PDK #MPW #BICMOS
@fpgasic
2,655
FPG𝔸SIC

27 Jun, 07:11

DUTCTL: A Flexible Open-Source Framework for Rapid Bring-Up, Characterization, and Remote Operation of Custom-Silicon RISC-V SoCs

https://pulp-platform.org/docs/riscvmunich2024/RISCV_europe_summit_2024_DUTCTL_poster.pdf

@vlsihub
2,595
FPG𝔸SIC

07 Mar, 08:52

CompressedLUT - a tool for lossless compression of lookup tables and generation of their hardware files in Verilog and C++ for RTL and HLS designs.

Links:
📄 https://doi.org/10.1145/3626202.3637575
💾 https://github.com/kiabuzz/CompressedLUT

#acceleration #LUT #lookuptable #lossless #compression #table-size-reduction #table-based-function-implementation
@fpgasic
3,803
FPG𝔸SIC

24 Nov, 08:49

Ramulator v2 - a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques).

Ramulator 2.0 provides the DRAM models for the following standards:
▫️DDR3, DDR4, DDR5
▫️LPDDR5
▫️GDDR6
▫️HBM2, HBM3

Links:
📄 https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
💾 https://github.com/CMU-SAFARI/ramulator2

#ram #model #dram #ddr #hbm
@fpgasic
4,645
FPG𝔸SIC

21 Nov, 09:21

Ramulator - a Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies, and various academic proposals.

Ramulator supports a wide array of commercial DRAM standards:
▫️DDR3, DDR4
▫️LPDDR3, LPDDR4
▫️GDDR5
▫️WIO, WIO2
▫️HBM
▫️SALP
▫️TL-DRAM
▫️RowClone
▫️DSARP

Links:
📄 http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
💾 https://github.com/CMU-SAFARI/ramulator

#ram #model #dram #ddr #hbm
@fpgasic
5,247
FPG𝔸SIC

02 Nov, 16:48

Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.

💾 https://arxiv.org/abs/2305.09580

@vlsihub
3,075
FPG𝔸SIC

27 Oct, 05:06

OpenVAF - an innovative Verilog-A compiler for use in circuit simulator. The major aim of this Project is to provide a high-quality standard compliant compiler for Verilog-A.

Features:
▫️fast compile times (usually below 1 second for most compact models)
▫️high-quality user interface
▫️easy setup
▫️fast simulations surpassing existing solutions by 30%-60%

OpenVAF currently contains the following useable projects:
1️⃣ VerilogAE allows obtaining model equations (calculates the value of a single Variable) from Verilog-A files
2️⃣ Melange is an experimental circuit simulator that leverage OpenVAF to gain access to compact models

Links:
📄 openvaf.semimod.de/
💾 github.com/pascalkuthe/OpenVAF

#simulation #model #veriloga
@fpgasic
3,338
FPG𝔸SIC

09 Oct, 16:27

Open-source IC cells as 3D prints. A rough how-to guide

This util can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used.

📄 https://medium.com/@thorstenknoll/open-source-ic-cells-as-3d-prints-a-rough-how-to-guide-90a8bc8b3b57
💾 https://github.com/trilomix/GDS3D

@vlsihub
3,175
FPG𝔸SIC

25 Aug, 07:40

VeriGen: A Large Language Model for Verilog Code Generation

The next step getting a Verilog fine-tuned LLM to generate the RTL; then we can kick-back & watch the whole SoC emerge autonomously. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation.

💾 https://arxiv.org/abs/2308.00708

#verilog #sv #codegen #llm
@fpgasic
3,897
FPG𝔸SIC

11 Feb, 11:40

VCD command line viewer for Windows, Linux and MacOS

Features:
▫️Outputs in YAML format
▫️Querying (unix pipe)
▫️Styling
▫️Auto-Refresh


💾 https://github.com/yne/vcd

#vcd #dump #waveform #testbench #waves #documentation
@fpgasic
5,088
FPG𝔸SIC

06 Dec, 18:23

Rosetta - Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

It contains six fully-developed applications from machine learning and image/video processing domains, where each benchmark consists multiple compute kernels that expose diverse sources of parallelism.

These applications are developed under realistic design constraints, and are optimized at both kernel-level and application-level with the advanced features of HLS tools to meet these constraints.

💾 Code
📄 Paper


#hls #fpga #benchmark
@fpgasic
5,331
FPG𝔸SIC

07 Oct, 17:49

#fridaymeme
@fpgasic
5,089
FPG𝔸SIC

12 Sep, 06:20

sv2chisel - SystemVerilog to Chisel Translator

💾 Code
📄 Paper
📄 Features & Limitations

#SV #verilog #chisel #translator

@embedoka
5,256
FPG𝔸SIC

09 Sep, 12:04

#fridaymeme
@fpgasic
4,596
FPG𝔸SIC

30 Aug, 10:54

Versatile list of HDL lint tools

📄 https://airhdl.com/blog/2017/02/08/fpga-lint-tools/
(updated August 2022)

#lint #linter #sv #verilog #vhdl
@fpgasic
4,594

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